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TB6560HQ/fg 2006-05-31 1 toshiba bicd integrated ci rcuit silicon monolithic TB6560HQ,tb6560fg pwm chopper-type bipolar stepping motor driver ic the TB6560HQ/fg is a pwm chopper-type sinusoidal micro-step bipolar stepping motor driver ic. it supports both 2-phase/1-2-phase/w1-2-phase/2w1-2-phase excitation mode and forward/reverse mode and is capable of low-vibration, high-performance drive of 2-phase bipolar type stepping motors using only a clock signal. features ? single-chip bipolar sinusoida l micro-step stepping motor driver ? uses high withstand vo ltage bicd process: ron (upper ? lower) = 0.6 ? (typ.) ? forward and reverse rotation control available ? selectable phase drive (2, 1-2, w1-2, and 2w1-2) ? high output withstand voltage: v ceo = 40 v ? high output current: i out = hq: 3.5 a (peak) fg: 2.5 a (peak) ? packages: hzip25-p-1.27/hqfp64-p-1010-0.50 ? built-in input pull-down resistor: 100 k ? (typ.) ? output monitor pin equipped: mo current (i mo (max) = 1 ma) ? equipped with reset and enable pins ? built-in overheat protection circuit * : since this product has a mos structure, it is sensitive to electrostatic disch arge. these ics are highly sensitive to electrostatic discharge. when handling them, please be careful of electrostatic discharge, temperature and humidity conditions. TB6560HQ tb6560fg weight: hzip25-p-1.27: 9.86 g (typ.) hqfp64-p-1010-0.50: 0.26 g (typ.) preliminar y the TB6560HQ/fg is a pb-free product. the following conditions apply to solderability: * solderability 1. use of sn-63pb solder bath * solder bath temperature = 230c * dipping time = 5 seconds * number of times = once * use of r-type flux 2. use of sn-3.0ag-0.5cu solder bath * solder bath temperature = 245c * dipping time = 5 seconds * the number of times = once * use of r-type flux
TB6560HQ/fg 2006-05-31 2 block diagram m1 m2 cw/ccw clk reset enable dcy1 dcy2 osc input circuit osc v dd maximum current setting circuit current selector circuit b overheat protection circuit protect m o + + bridge driver a decode r v ma out_ap out_am n fa v mb bridge driver b b decode r out_bp out_bm n fb tq1 tq2 sgnd pgnda pgndb current selector circuit a 10/1 1/42 2/43 11/2, 3, 4 9/61, 62 12/6, 7 8/55, 56 14/13, 14, 15 13/10, 11 16/19, 20 18/25, 26 17/23 19/28 20/30, 31 23/36 22/35 21/33 3/45 5/48 4/47 25/39 24/38 7/53 15/16 6/50, 51 TB6560HQ/tb6560fg
TB6560HQ/fg 2006-05-31 3 pin functions pin no. hq fg i/o symbol functional description 1 42 input tq2 torque setting input (current setting) (built-in pull-down resistor) 2 43 input tq1 torque setting input (current setting) (built-in pull-down resistor) 3 45 input clk step transition, clock input (built-in pull-down resistor) 4 47 input enable h: enable; l: all output off (built-in pull-down resistor) 5 48 input reset l: reset (output is reset to its init ial state) (built-in pull-down resistor) 6 50/51 ? sgnd signal ground (control side) (note 1) 7 53 ? osc connects to and oscill ates cr. output chopping. 8 55/56 input v mb motor side power pin (b phase side) (note 1) 9 61/62 output out_bm out_b output (note 1) 10 1 ? pgndb power ground 11 2/3/4 ? n fb b channel output current detecti on pin (resistor connection). short the two pins for fg. (note 1) 12 6/7 output out_bp out_b output (note 1) 13 10/11 output out_am out_a output (note 1) 14 13/14/15 ? n fa a channel output current detecti on pin (resistor connection). short the two pins for fg. (note 1) 15 16 ? pgnda power ground 16 19/20 output out_ap out_a output (note 1) 17 23 output m o initial state detection output. on when in initial state (open drain). 18 25/26 input v ma motor side power pin (a phase side) (note 1) 19 28 output protect when tsd, on (open drain). normal z. 20 30/31 input v dd control side power pin. (note 1) 21 33 input cw/ccw forward/reverse toggle pin. l: forward; h: reverse (built-in pull-down resistor) 22 35 input m2 excitation mode setting input (built-in pull-down resistor) 23 36 input m1 excitation mode setting input (built-in pull-down resistor) 24 38 input dcy2 current decay mode setting input (built-in pull-down resistor) 25 39 input dcy1 current decay mode setting input (built-in pull-down resistor) hq: no non-connection (nc) fg: other than the above pins, all are nc (since nc pins are not connected to the internal circuit, a potential can be applied to those pins.) all control input pins: pull-down resistor 100 k ? (typ.) note 1: if the fg pin number column indicates more than on e pin, the indicated pins should be tied to each other at a position as close to the pins as possible. (the electrical characteristics of the relevant pins in this document refer to those when they are handled in that way.) input pins (m1, m2, clk, cw/ccw, enable and reset) output ins (mo, protect) v dd 100 k ? 100 ? 100 ?
TB6560HQ/fg 2006-05-31 4 absolute maximum ratings (ta = 25c) characteristic symbol rating unit v dd 6 power supply voltage v ma/b 40 v hq 3.5 output current peak fg i o (peak) 2.5 a/phase mo drain current i (mo) 1 ma input voltage v in 5.5 v 5 (note 1) hq 43 (note 2) 1.7 (note 3) power dissipation fg p d 4.2 (note 4) w operating temperature t opr ? 30 to 85 c storage temperature t stg ? 55 to 150 c note 1: ta = 25c, no heat sink. note 2: ta = 25c, with infinite heat sink (hzip25). note 3: ta = 25c, with soldered leads. note 4: ta = 25c, when mounted on the board (4-layer board). susceptible to the board layout and the mounting conditions. operating range (ta = ? 20 to 85c) characteristic symbol test condition min typ. max unit v dd ? 4.5 5.0 5.5 v power supply voltage v ma/b v ma/b > = ? 26.4 v hq ? ? ? 3 output current fg i out ? ? 1.5 a input voltage v in ? 0 ? 5.5 v clock frequency f clk ? ? ? 15 khz osc frequency f osc ? ? ? 600 khz
TB6560HQ/fg 2006-05-31 5 electrical characteristics (ta = 25c, v dd = 5 v, v m = 24 v) characteristic symbol test circuit test condition min typ. max unit high v in (h) 2.0 ? v dd input voltage low v in (l) 1 ? 0.2 ? 0.8 v input hysteresis voltage v h 1 m1, m2, cw/ccw, clk, reset , enable, decay, tq1, tq2, isd ? 400 ? mv i in (h) m1, m2, cw/ccw, clk, reset , enable, decay, tq1, tq2, isd v in = 5.0 v built-in pull-down resistor 30 55 80 input current i in (l) 1 v in = 0 v ? ? 1 a i dd1 output open, reset : h, enable: h (2, 1-2 phase excitation) ? 3 5 i dd2 output open, reset : h, enable: h (w1 ? 2, 2w1-2 phase excitation) ? 3 5 i dd3 reset : l, enable: l ? 2 5 consumption current v dd pin i dd4 1 reset : h, enable: l ? 2 5 ma i m1 reset : h/l, enable: l ? 0.5 1 consumption current v m pin i m2 1 reset : h/l, enable: h ? 0.7 2 ma output channel margin of error ? v o ? b/a, c osc = 0.0033 f ? 5 ? 5 % v nfhh tq1 = h, tq2 = h 10 20 30 v nfhl tq1 = l, tq2 = h 47 50 55 v nflh tq1 = h, tq2 = l 70 75 80 vnf level level differential v nfll ? tq1 = l, tq2 = l 100 % minimum clock pulse width t w (clk) ? ? ? 100 ? ns mo output residual voltage v ol mo ? i ol = 1 ma ? ? 0.5 v tsd tsd ? (design target value) ? 170 ? c tsd hysteresis tsdhys ? (design target value) ? 20 ? c oscillating frequency f osc c = 330 pf 60 130 200 khz
TB6560HQ/fg 2006-05-31 6 electrical characteristics (ta = 25c, v dd = 5 v, v m = 24 v) output block characteristic symbol test circuit test condition min typ. max unit ron u1h ? 0.3 0.4 hq ron l1h i out = 1.5 a ? 0.3 0.4 ron u1f ? 0.35 0.5 output on resistor fg ron l1f 4 i out = 1.5 a ? 0.35 0.5 ? 2w1-2- phase excitation w1-2- phase excitation 1-2- phase excitation = 0 ? 100 ? 2w1-2- phase excitation ? ? = 1/8 93 98 100 2w1-2- phase excitation w1-2- phase excitation ? = 2/8 87 92 97 2w1-2- phase excitation ? ? = 3/8 78 83 88 2w1-2- phase excitation w1-2- phase excitation 1-2- phase excitation = 4/8 66 71 76 2w1-2- phase excitation ? ? = 5/8 51 56 61 2w1-2- phase excitation w1-2- phase excitation ? = 6/8 33 38 43 2w1-2- phase excitation ? ? = 7/8 15 20 25 a-b chopping current (note) 2-phase excitation vector ? ? tq1 = l, tq2 = l ? 100 ? % reference voltage v nf ? tq1, tq2 = l (100%) osc = 100 khz 450 500 550 mv t r ? 0.1 ? output transistor switching characteristics t f r l = 2 ? , v nf = 0 v, c l = 15 pf ? 0.1 ? t plh reset to output ? 0.1 ? t plh ? 0.3 ? delay time t phl 7 enable to output ? 0.2 ? s upper side i lh ? ? 1 output leakage current lower side i ll 6 v m = 40 v ? ? 1 a note: maximum current ( = 0): 100%
TB6560HQ/fg 2006-05-31 7 description of functions 1. excitation settings you can use the m1 and m2 pin settings to configure fo ur different excitation settings. (the default is 2-phase excitation using the internal pull-down.) input m2 m1 mode (excitation) l l 2-phase l h 1-2-phase h l w1-2-phase h h 2w1-2-phase 2. function when the enable signal goes low level, it sets an off on the output. the outp ut changes to the initial mode shown in the table below when the reset signal goes low level. in this mode, the status of the clk and cw/ccw pins are irrelevant. input clk cw/ccw reset enable output mode l h h cw h h h ccw x x l h initial mode x x x l z x: don?t care 3. initial mode when reset is used, the phase currents are as follows. in this instance, the mo pin is l (connected to open drain). excitation mode a phase current b phase current 2-phase 100% ? 100% 1-2-phase 100% 0% w1-2-phase 100% 0% 2w1-2-phase 100% 0% 4. current decay settings output is generated by four pwm blasts; 25% decay is created by inducing decay during the last blast in fast mode; 50% decay is created by inducing decay during the last two blasts in fast mode; and 100% decay is created by inducing all four blasts in fast mode. if there is no input with the pull-down resi stor connection then the setting is normal. dcy2 dcy1 current decay setting l l normal 0% l h 25% decay h l 50% decay h h 100% decay
TB6560HQ/fg 2006-05-31 8 5. torque settings (current value) the current ratio used in actual operations is determined in regard to the current setting due to resistance. configure this for extremely low torque scenarios su ch as when weak excitation mode is stopped. if there is no input with the pull-down resistor connection then the setting is 100% torque. tq2 tq1 current ratio l l 100% l h 75% h l 50% h h 20% (weak excitation) 6. protect and mo (output pins) you can configure settings from the receiving side by using an open-drain connection for the output pins and making the pull-up voltage variable. when a given pin is in its designated stat e it will go on and output at low level. pin state protect mo low overheat protection operation initial state z normal operation other than initial state 7. osc output chopping waves are generated by connect ing the condenser and having the cr oscillate. the values are as shown below (roughly: 30% margin of error). condenser oscillating frequency 1000 pf 44 khz 330 pf 130 khz 100 pf 400 khz open-drain connection
TB6560HQ/fg 2006-05-31 9 relationship between enable, reset and output (out and mo) ex-1: enable 1-2-phase excitation (m1: h, m2: l) the enable signal at low level disables only the ou tput signals. internal logic functions proceed in accordance with input clock signals and without regard to the enable signal. therefore output current is initiated by the timing of the internal lo gic circuit after release of disable mode. ex-2: reset 1-2-phase excitation (m1: h, m2: l) when the reset signal goes low level, output goes initial st ate and the mo output goes low level (initial state: a channel output current is 100%). once the reset signal returns to high level, output conti nues from the next state after initial from the next raise in the clock signal. clk enable reset mo 100 (%) 0 ? 100 t 0 t 1 t 2 t 3 t 7 t 8 t 9 t 10 t 11 t 12 off 71 ? 71 i a cw clk enable reset mo 100 (%) 0 ? 100 t 0 t 1 t 2 t 3 t 7 t 8 t 4 t 5 t 2 t 3 71 ? 71 t 6 i a cw
TB6560HQ/fg 2006-05-31 10 2-phase excitation (m1: l, m2: l, cw mode) 1-2-phase excitation (m1: h, m2: l, cw mode) clk mo 100 (%) 0 ? 100 t 0 t 1 t 2 t 3 t 7 t 4 t 5 t 6 i a cw 100 (%) 0 ? 100 i b clk mo 100 (%) 0 ? 100 t 0 t 1 t 2 t 3 t 7 t 8 t 4 t 5 t 6 71 ? 71 i a 100 (%) 0 ? 100 71 ? 71 i b cw
TB6560HQ/fg 2006-05-31 11 w1-2-phase excitation (m1: l, m2: h, cw mode) clk mo t 0 t 1 t 2 t 3 t 7 t 4 t 5 t 6 cw 100 (%) 92 71 38 0 ? 38 ? 71 ? 92 ? 100 i a t 8 t 12 t 13 t 9 t 10 t 11 t 14 t 15 t 16 100 (%) 92 71 38 0 ? 38 ? 71 ? 92 ? 100 i b
TB6560HQ/fg 2006-05-31 12 2w1-2-phase excitation (m1: h, m2: h, cw mode) i b i a clk t 0 t 1 t 2 t 3 t 7 t 8 t 4 t 5 t 12 t 13 t 6 cw mo 100 (%) 98 92 83 71 56 38 20 0 ? 20 ? 38 ? 56 ? 71 ? 83 ? 92 ? 98 ? 100 100 (%) 98 92 83 71 56 38 20 0 ? 20 ? 38 ? 56 ? 71 ? 83 ? 92 ? 98 ? 100 t 9 t 10 t 11 t 14 t 17 t 18 t 15 t 16 t 19 t 20 t 21 t 22 t 23 t 27 t 28 t 24 t 25 t 26 t 29 t 30 t 31 t 32
TB6560HQ/fg 2006-05-31 13 it is recommended that m1 and m2 signals be changed after setting the reset signal low during the initial state (mo is low). even when the mo is low, changi ng the reset signal without setting the reset signal low may cause the discontinuity in the current waveform. ck mo m2 100 (%) 0 1-2-phase excitation 91 i a 71.4 40 ? 40 ? 71.4 ? 91 ? 100 m1 reset w1-2-phase excitation
TB6560HQ/fg 2006-05-31 14 1. current waveform and settings of mixed decay mode you can configure the points of the current?s shaped width (current?s pulsating flow) using 1-bit input in decay mode for constant-current control. ?nf? refers to the point at which the output current reaches its settin g current value and ?rnf? refers to the monitoring timing of the setting current. the smaller the mdt value, the smaller the current ripple (current wave peak), and the current?s decay capability will fall. nf normal mode rnf setting current value osc pin internal waveform f chop nf 25% decay mode rnf mdt setting current value nf 50% decay mode rnf mdt setting current value nf 100% decay mode rnf setting current value charge mode nf: setting current value reached slow mode current monitoring (when setting current value > output current) charge mode charge mode nf: setting current value reached slow mode mixed decay timing fast mode current monitoring (when setting current value > output current) charge mode charge mode nf: setting current value reached slow mode mixed decay timing fast mode current monitoring (when setting current value > output current) charge mode charge mode nf: setting current value reached fast mode current monitoring (when setting current value > output current) charge mode
TB6560HQ/fg 2006-05-31 15 2. current control modes (decay mode effect) ? direction in which current value increases (sine wave) ? direction in which sine wave decreases (when a high decay ratio (mdt%) is used in mixed decay mode) ? direction in which sine wave decreases (when a low decay ratio (mdt%) is used in mixed decay mode) during mixed decay mode and fast decay mode, if th e setting current value < output current at rnf: current monitoring point, the charge mode at the next chopping cycl e will disappear and the pattern will change to slow ? fast mode (slow fast occurs at mdt). (in reality, a charge is applied momentarily to confirm the current.) note: these figures are intended for illustrative purposes only. if designed more realistically, they would show transient response curves. slow slow slow slow fast fast charge charge fast charge fast charge setting current value setting current value slow slow fast charge fast charge slow fast slow fast charge since the current?s rate of decay is fast, its compliance with the setting current value is also fast. setting current value setting current value slow fast charge slow fast charge fast slow fast slow since the current?s rate of decay is slow, its compliance with the setting current value takes a long time (or may not follow at all). setting current value setting current value
TB6560HQ/fg 2006-05-31 16 3. mixed decay mode waveform (current waveform) ? when the nf points come after mixed decay timing ? when the output current value > setting current value in mixed decay mode * : even if the output current rises above the setting current at the rnf point, a charge is applied momentarily to confirm the current. nf nf 25% mixed decay mode osc pin internal waveform i out f chop f chop setting current value setting current value rnf mdt (mixed decay timing) points nf nf 25% mixed decay mode i out f chop f chop setting current value setting current value rnf mdt (mixed decay timing) points clk signal input switches to fast mode after charge mode rnf nf nf 25% mixed decay mode i out f chop f chop setting current value clk signal input f chop mdt (mixed decay timing) points setting current value rnf rnf
TB6560HQ/fg 2006-05-31 17 4. fast decay mode waveform after the current value set by rnf, torque or other means is attained, the output current to load will make the transition to full regenerative mode. f chop clk signal input fast decay mode (100% decay mode) setting current value i out nf since the setting current value > output current, charge mode nf fast decay mode transition will take place at even the next cycle. rnf rnf rnf setting current value transition to charge mode for a brief moment
TB6560HQ/fg 2006-05-31 18 5. clk signal and internal cr ck output current waveform (when the clk signal is input in the middle of slow mode) when the clk signal is input, the chopping counter (osc counter) is forcibly reset at the timing of the osc. as a result, the response to input data is fast in comparison to methods that don?t reset the counter. the delay time is one osc cycle: 10 s @100 khz chopping using the logic block logic value. after the osc counter is reset by clk signal input, the transition is invariably made to charge mode for a brief moment to compare the current. note: even in fast decay mode, the transition is invariably made to charge mode for a brief moment to compare the current. 25% mixed decay mode clk signal input setting current value i out rnf setting current value f chop osc pin internal waveform transition to charge mode for a brief moment the cr counter is reset here. nf rnf mdt nf mdt f chop f chop
TB6560HQ/fg 2006-05-31 19 6. clk signal and internal osc output current waveform (when the clk signal is input in the middle of charge mode) 25% mixed decay mode clk signal input setting current value i out rnf setting current value f chop osc pin internal waveform transition to charge mode for a brief moment the osc counter is reset here. nf rnf mdt mdt f chop f chop
TB6560HQ/fg 2006-05-31 20 7. clk signal and internal osc output current waveform (when the clk signal is input in the middle of fast mode) nf 25% mixed decay mode clk signal input setting current value i out rnf setting current value f chop osc pin internal waveform transition to charge mode for a brief moment the osc counter is reset here. f chop f chop mdt nf rnf mdt
TB6560HQ/fg 2006-05-31 21 8. internal osc output current waveform when setting current is reverse (when the clk signal is input using 2-phase excitation) 25% mixed decay mode clk signal input f chop the osc counter is reset here. f chop f chop setting current value i out rnf setting current value nf rnf 0 mdt nf
TB6560HQ/fg 2006-05-31 22 current draw-out path when en able is input in mid operation when all the output transistors ar e forced off during slow mode, the coil energy is drawn out in the following modes: note: parasitic diodes are indicated on the designed li nes. however, these are not normally used in mixed decay mode. as shown in the figure above, an outp ut transistor has parasitic diodes. normally, when the energy of the coil is drawn out, each transistor is tu rned on and the power flows in the opposite-to-normal direction; as a result, the parasi tic diode is not used. however, when all the output transistors are forced off, the coil energy is drawn out via the parasitic diode. u1 l1 u2 l2 pgnd off off u1 l1 u2 l2 off on note load pgnd u1 l1 u2 l2 off off note load pgnd note r nf v m on on load charge mode slow mode force off mode on r nf v m r nf v m off off enable is input off
TB6560HQ/fg 2006-05-31 23 output stage transistor operation mode output stage transistor operation functions clk u1 u2 l1 l2 charge on off off on slow off off on on fast off on on off note: the above chart shows an example of when the current flows as indicated by the arrows in the above figures. if the current flows in the opposite di rection, refer to the following chart: clk u1 u2 l1 l2 charge off on on off slow off off on on fast on off off on upon transitions of above-mentioned functions, a dead time of about 300 ns is inserted respectively. u1 l1 u2 l2 pgnd off off u1 l1 u2 l2 off on note load pgnd u1 l1 u2 l2 note load pgnd note r nf v m on on load charge mode slow mode fast mode on r nf v m r nf v m off off off on on
TB6560HQ/fg 2006-05-31 24 measurement waveform figure 1 timing waveforms and names osc-charge delay: the conversion from the osc waveform to the internal osc waveform is done by recognizing the level of chopping wave. the voltages of 2 v or above are considered as a high level, and voltages of 0.5 v or below are considered as a low level as designed values. however, there is a response delay and that there occurs the peak-to-peak voltage variation. figure 2 timing waveforms and names (cr and output) clk t clk t clk t plh t phl v m gnd t r t f 10% 50% 90% 90% 50% 10% osc waveform osc pin internal waveform 2 v 0.5 v
TB6560HQ/fg 2006-05-31 25 power dissipation TB6560HQ
TB6560HQ/fg 2006-05-31 26 1. how to turn on the power turn on v dd . when the voltage has stabilized, turn on v ma/b . in addition, set the control input pins to low when inputting the power. (all the control input pins ar e pulled down internally.) once the power is on, the clk signal is received and excitation advances when reset goes high and excitation is output when enable goes high. if only reset goes high, excitation won't be output and only the internal counter will advance. likewise, if only enable goes high, exci tation won't advance even if the clk signal is input and it will remain in the initial state. the following is an example: 2. calculating the setting current to perform constant-current operations, it is necessary to configure the base current using an external resistor. if the voltage on the n fa (b) pin is 0.5 v (with a torque of 100%) or greater, it will not charge. ex.: if the maximum current va lue is 1 a, the external resistance will be 0.5 w. 3. pwm oscillator frequency (external condenser setting) an external condenser connected to the osc pin is used to internally generate a saw tooth waveform. pwm is controlled using this frequency. toshiba recommends 100 to 3300 pf for the capacitance, taking variations between ics into consideration. approximation: f osc = 1/(c osc 1.5 (10/c osc + 1)/66) 1000 khz 4. power dissipation the ic power dissipation is determ ined by the following equation: p = v dd i dd + i out ron 2 drivers the higher the ambient temperature, the smaller the power dissipation. check the pd-ta curve, and be su re to design the heat dissipation with a sufficient margin. 5. heat sink fin processing the ic fin (rear) is electrically connected to the rear of the chip. if current fl ows to the fin, the ic will malfunction. if there is any possibili ty of a voltage being generated betw een the ic gnd and the fin, either ground the fin or insulate it. output z z output current setting internal current setting out enable h l h l reset h l clk internal current setting: invariable output off internal current setting: variable
TB6560HQ/fg 2006-05-31 27 6. thermal protection when the temperature reaches 170c (as standard value), the thermal protection circuit is activated switching the output to off. there is a variation of plus or minus about 20c in the temperature that triggers the circuit operation.
TB6560HQ/fg 2006-05-31 28 nfcompa m mcu or external input clk reset enable m1 m2 cw/ccw dcy1 dcy2 tq1 tq2 protect mo r1 r2 osc 100 pf ? f 5 v 1 f v dd v ma v mb 1 f 47 f 24 v logic current control h-sw a h-sw b outap outam outbp outbm rnfa rnfb n fa n fb nfcompb 0.5 ? : ioutmax = 1.0 a
TB6560HQ/fg 2006-05-31 29 package dimensions weight: 9.86 g (typ.)
TB6560HQ/fg 2006-05-31 30 package dimensions weight: 0.26 g (typ.) note: the rear heat sink block will be 5.5 mm 5.5 mm. (provisional)
TB6560HQ/fg 2006-05-31 31 restrictions on product use 060116eba ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their i nherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshiba products specific ations. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconduct or devices,? or ?toshiba semiconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are in tended for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfuncti on or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage incl ude atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traf fic signal instruments, comb ustion control instruments, medical instruments, all types of safety devices, et c. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_q ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringement s of patents or other rights of the third parties which may result from its use. no license is granted by implicat ion or otherwise under any pa tent or patent rights of toshiba or others. 021023_c ? the products described in this document are subject to the foreign exchange and foreign trade laws. 021023_e

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